1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device that uses a non-volatile variable resistance element configured by a first electrode, a second electrode, and a variable resistor interposed between the two electrodes for storing information.
2. Description of the Related Art
In the recent years, as a next-generation non-volatile random access memory (NVRAM: Non-volatile Random Access Memory) that takes place of a flash memory and is capable of a high-speed operation, various device structures such as FeRAM (Ferroelectric RAM), MRAM (Magnetic RAM), PRAM (Phase Change RAM), and the like have been proposed, and an intense competition in development is under progress from viewpoints of improving performance, increasing reliability, lowering costs, and process consistency.
With respect to these known techniques, there is proposed a resistance non-volatile memory RRAM (Resistive Random Access Memory) using a variable resistance element that reversibly changes its electric resistance by applying a voltage pulse. A configuration thereof is shown in FIG. 17.
As shown in FIG. 17, a variable resistance element of the conventional configuration has a structure in which a lower electrode 103, a variable resistor 102, and an upper electrode 101 are laminated in order, and has a property of being capable of reversibly changing a resistance value by applying a voltage pulse between the upper electrode 101 and the lower electrode 103. The configuration is such that a new non-volatile semiconductor memory device can be realized by reading the resistance value that changes due to this reversible resistance changing operation (hereinafter, referred to as “switching operation”).
The above non-volatile semiconductor memory device has a memory cell array formed by arranging a plurality of memory cells, including variable resistance elements, in a matrix respectively in a row direction and a column direction, and is configured by arranging a peripheral circuit that controls programming, erasing, and reading operations of data with respect to each memory cell in the memory cell array. Further, as such a memory cell, there are a (so-called “1T1R type”) memory cell configured by one selection transistor T and one variable resistance element R, a (so-called “1R type”) memory cell configured by only one variable resistance element R, and the like based on a difference in their components. Among those, a configuration example of the 1T1R type memory cell is shown in FIG. 18.
FIG. 18 is an equivalent circuit diagram of a configuration example of a memory cell array formed of the 1T1R type memory cells. A gate of the selection transistor T of each memory cell is connected to a word line (WL1 to WLn), and a source of the selection transistor T of each memory cell is connected to a source line (SL1 to SLn) (n is a natural number). Further, one electrode of the variable resistance element R of each memory cell is connected to a drain of the selection transistor T, and the other electrode of the variable resistance element R is connected to a bit line (BL1 to BLm) (m is a natural number). Moreover, the respective word lines WL1 to WLn are connected to a word line decoder 106, the respective source lines SL1 to SLn are connected to a source line decoder 107, and the respective bit lines BL1 to BLm are connected to a bit line decoder 105. Further, the configuration is such that a particular bit line, word line, and source line for the programming, erasing, and reading operations on a particular memory cell in a memory cell array 104 are selected in accordance with an address input (not shown).
FIG. 19 is a schematic cross-sectional diagram of a memory cell configuring the memory cell array 104 of FIG. 18. In the present configuration, the selection transistor T and the variable resistance element R forms one memory cell. The selection transistor T is configured by a gate insulating film 113, a gate electrode 114, and a drain diffusion layer region 115 and a source diffusion layer region 116, and is formed on an upper surface of a semiconductor substrate 111 in which element isolating regions 112 are formed. Moreover, the variable resistance element R is configured by a lower electrode 118, a variable resistor 119, and an upper electrode 120.
Further, the gate electrode 114 of the transistor T configures the word line, and a source line wiring 124 is electrically connected to the source diffusion layer region 116 of the transistor T via a contact plug 122. Moreover, a bit line wiring 123 is electrically connected to the upper electrode 120 of the variable resistance element R via a contact plug 121, while the lower electrode 118 of the variable resistance element R is electrically connected to the drain diffusion layer region 115 of the transistor T via a contact plug 117.
With the configuration in which the selection transistor T and the variable resistance element R are arranged in series, the transistor of the memory cell that is selected by a potential change in the word line is caused to be in an ON state, and further, the programming or erasing can selectively be performed only on the variable resistance element R of the memory cell that is selected by a potential change in the bit line.
FIG. 20 is an equivalent circuit diagram of a configuration example of the 1R type memory cells. Each of the memory cells is configured only by the variable resistance element R, and one electrode of the variable resistance element R is connected to the word line (WL1 to WLn), and the other electrode thereof is connected to the bit line (BL1 to BLm). Further, the respective word lines WL1 to WLn are connected to the word line decoder 106, and the respective bit lines BL1 to BLm are connected to the bit line decoder 105. Further, the configuration is such that a particular bit line and word line for the programming, erasing, and reading operations on a particular memory cell in a memory cell array 131 are selected in accordance with the address input (not shown).
FIG. 21 is a perspective schematic structural diagram of an example of the memory cells configuring the memory cell array 131 of FIG. 20. As shown in FIG. 21, upper electrode wirings 132 and lower electrode wirings 133 are arranged so as to intersect each another, and one of the upper electrode wirings 132 and lower electrode wirings 133 form the bit lines, and the other of the upper electrode wirings 132 and lower electrode wirings 133 form the word lines. Moreover, it has a structure in which a variable resistor 134 is arranged at a point where respective electrodes intersect (typically referred to as a “cross point”). In the example of FIG. 21, for the sake of convenience, the upper electrode 132 and the variable resistor 134 are formed into the same shape, however, a portion of the variable resistor 134 that electrically contributes in the switching operation is the region of the cross point where the upper electrode 132 and the lower electrode 133 intersect each another.
Note that, as a variable resistor material used for the variable resistor 119 in FIG. 19 or the variable resistor 134 in FIG. 21, a method of reversibly changing the electric resistance by applying a voltage pulse on a Perovskite material that is known for its colossal magnet resistance effect is disclosed by Shangquing Liu, Alex Ignatiev et al. of University of Houston, U.S.A., in U.S. Pat. No. 6,204,139 as well as in Liu, S. Q et al., “Electric-pulse-induced reversible resistance change effect in magnetoresistive films”, Applied Physics Letter, Vol. 76, pp. 2749-2751, 2000. Despite the usage of the Perovskite material that is known for its colossal magnet resistance effect, this method exhibits a resistance change of several orders even at a room temperature without any application of a magnetic field. In an element structure exemplified in U.S. Pat. No. 6,204,139, a film of praseodymium calcium manganese oxide Pr1-xCaxMnO3 (PCMO) that is a Perovskite-type oxide is used as the material of the variable resistor.
Moreover, as other variable resistor materials, oxides of transition metal elements such as a titanium oxide (TiO2) film, a nickel oxide (NiO) film, a zinc oxide (ZnO) film, and a niobium oxide (Nb2O5) film are known to exhibit reversible resistance change from H. Pagnia at al., “Bistable Switching in Electroformed Metal-Insulator-Metal Devices”, Phys. Stat. Sol. (a), vol. 108, pp. 11-65, 1988 and Back, I. G. et al., “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses”, IEDM 04, pp. 587-590, 2004, and the like.
Further, the variable resistance elements in which the resistance change occurs exhibit n-type or p-type semiconductor conductivity by having an impurity level caused by oxygen defects in the metal oxide formed in a band gap. Further, the resistance change is confirmed as being a state change in the vicinity of an electrode interface.
In order to stably perform resistance switching of the variable resistance elements having the above transition metal oxides as the variable resistor, it is preferable to use only one of the two electrode interfaces of the variable resistance element as the switching region. Therefore, it is preferable to use different electrodes for the electrode materials on both ends, form a non-switching interface by making an ohmic contact at an interface with one electrode, and form a switching interface by making e.g. a Schottky barrier junction at an interface with the other electrode.
When the transition metal oxide is used as the variable resistor, an initial resistance of the variable resistance element just after a production is extremely high; and in order to bring it to a state in which switching between a high resistance state and a low resistance state is possible by an electric stress, there needs to be formed, prior to an actual use, a current path (hereinafter, suitably referred to as a “filament path”) in which the resistance switching occurs by applying a voltage pulse having a larger voltage amplitude and a longer pulse width than a voltage pulse that is used in a normal writing operation to the variable resistance element in the initial state. Such a process of forming the filament path in the variable resistor is called forming process. The electrical property of the element thereafter is determined by the filament path formed by this forming process.
The forming process is one kind of a soft breakdown, and control of current from the beginning of the breakdown greatly affects the formation of the filament path, that is, the electrical property of the element.
As a principle, current for operations of the switching element should be able to be arbitrarily controlled if the filament path is formed by controlling the current upon the forming by a current controlling element such as a transistor connected in series to an element. However, due to the extremely sharp current increase upon the breakdown, for example, in a case where a transistor is used, as shown in an equivalent circuit diagram of FIG. 22A, a sharp current flow that cannot be controlled by the transistor occurs under an influence of a parasitic capacitance Cj of the transistor. Therefore, the change in the current flowing in the element after completion of the forming is as shown in FIG. 22B. Due to this uncontrollable sharp current, which is called spike current, the formed filament varies among the elements, and it becomes extremely difficult to stably form elements with operational current at a predetermined value or less.
In contrast, there has been reported a method that obtains a property improvement by forming a buffer layer between the electrode and the metal oxide used as the variable resistor.
Japanese Unexamined Patent Publication No. 2008-306157 discloses a method in which, with respect to nickel oxide and cobalt oxide that are the metal oxides to be p-type semiconductors, Ta, Ti, Al, and the like, which form a Schottky barrier junction therewith, are formed as an electrode on a switching interface side, and thereby, these electrode metals form titanium oxide and tantalum oxide by taking a part of oxygen from nickel oxide and cobalt oxide due to having a higher ionization tendency than nickel and cobalt, and the titanium oxide and tantalum oxide serve as a buffer layer and suppress the spike current caused by the parasitic capacitance, and thus a variable resistance element that operates with a low current is formed. However, since the ionization tendency of the electrode metals is higher than that of the metal oxide film of the variable resistor, there is a problem that the element property varies because oxidation of the electrode material has progressed further than it had been set by continuation of the switching operation and a thermal history on the element.
In M. Terai et al., “Effect of Bottom Electrode of ReRAM with Ta2O5/TiO2 Stack on RTN and Retention”, IEDM 09, pp. 775-778, 2009 (hereinafter, referred to as “well-known reference 1”), there is disclosed a method of realizing an improvement of property by using titanium oxide that is an n-type metal oxide as a variable resistance material and inserting tantalum oxide between the variable resistance material and a non-switching side electrode. However, in the case of aiming to obtain a stable switching property by using titanium oxide as the variable resistance material, Pt and Ru having a sufficiently large work function is required to be used as the switching side electrode, and it becomes difficult to manufacture a device using an already-existing facility.